1. Field of the Invention
The present invention relates to a semiconductor memory device such as a pseudo static random access memory (pseudo SRAM), and in particular, to a semiconductor memory device provided with a control circuit for controlling a memory cell array in a non-normal operation mode, such as a test mode and a command mode, which is different from a normal operation mode for executing writing data into the memory cell array and reading out data from the memory cell array.
2. Description of the Prior Art
According to a prior art technique, a semiconductor memory device such as DRAM, which has a test mode and a command mode besides the normal operation mode, is constructed so as to operate in the normal operation mode in a state on the way to entry into the test mode or the command mode.
In the prototype stage of a so-called pseudo SRAM, which has DRAM type memory cells of the prior art technique and operates with each memory cell refresh timing decided internally independently of a signal from an external apparatus, the present inventor and others discovered the possibility of occurrence of destroyed cases when data are written into the memory cell array while operating in the normal operation mode in the state on the way to the entry into the test mode or the command mode. Moreover, in this case, there is such a problem that a control circuit sometimes becomes a freeze state due to timing shifts among a plurality of internal control signals.